hi, On the FPGA implementation of decimation filters, which type of decimate filters do you prefer? I am designing a IF DDC converter, and wana use FPGA to implement the decimate filter, but I found the Half-band lowpass and the euipripple fir filters can hardly stop the out-band below -80dB. I wish to stop the outband under -90dB, and the Chebyshev filter can, but it's not stable because it's IIR, so I appreciate FIR filters. Any suggestions? Sun Lei.

# on decimate filters

Started by ●January 1, 2007

Reply by ●January 1, 20072007-01-01

If you can't get the rejection, it is only because of constraints that you have and have failed to mention. You might want to explain in some detail what you are doing if you want to get some advice here. Dirk SunLei wrote:> hi, > > On the FPGA implementation of decimation filters, which type of decimate > filters do you prefer? > > I am designing a IF DDC converter, and wana use FPGA to implement the > decimate filter, but I found the Half-band lowpass and the euipripple fir > filters can hardly stop the out-band below -80dB. I wish to stop the outband > under -90dB, and the Chebyshev filter can, but it's not stable because it's > IIR, so I appreciate FIR filters. > > Any suggestions? > > Sun Lei.

Reply by ●January 1, 20072007-01-01

SunLei wrote:> hi, > > On the FPGA implementation of decimation filters, which type of decimate > filters do you prefer?The kind that are best for the project at hand.> > I am designing a IF DDC converter, and wana use FPGA to implement the > decimate filter, but I found the Half-band lowpass and the euipripple fir > filters can hardly stop the out-band below -80dB.Then you are using the wrong ones. Either of these topologies, given a long enough filter and deep enough word lengths, can meet just about any attenuation requirement you can cook up.> I wish to stop the outband > under -90dB, and the Chebyshev filter can, but it's not stable because it's > IIR, so I appreciate FIR filters. >IIR filters aren't _automatically_ unstable, they're just not guaranteed to be stable.> Any suggestions? > > Sun Lei.I'm with Dirk. Tell us what you're _really_ thinking, and why you can't do what you're trying to do with the tools that you have available. I suspect that you are laboring under one or both of the following two problems: 1. You're a raw beginner at DSP stuff, and you're trying to do design from inadequate cookbooks. This is inevitable, because cookbook design is nearly always inadequate for DSP design. 2. You have a relatively small gap between your required filter bandwidth and your required rejection band. This small gap is forcing you to seek a filter with a very small shape factor, which isn't addressed by your cookbooks. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ "Applied Control Theory for Embedded Systems" came out in April. See details at http://www.wescottdesign.com/actfes/actfes.html

Reply by ●January 2, 20072007-01-02

Hi, For IF DDC converter you can go with CIC filter followed by FIR filter. CIC filter does most of the decimation for you, and for the out-of-band suppression you can go with the FIR filter. CIC filter does not need any multipliers.... You can find lot of materials relating to design of CIC filter on the net. Best Regards, Arun SunLei wrote:> hi, > > On the FPGA implementation of decimation filters, which type of decimate > filters do you prefer? > > I am designing a IF DDC converter, and wana use FPGA to implement the > decimate filter, but I found the Half-band lowpass and the euipripple fir > filters can hardly stop the out-band below -80dB. I wish to stop the outband > under -90dB, and the Chebyshev filter can, but it's not stable because it's > IIR, so I appreciate FIR filters. > > Any suggestions? > > Sun Lei.

Reply by ●January 3, 20072007-01-03

Yes, the CIC fiter has good performance on high decimate rate, but not on low decimate rate. On low decimate rate. the filter passband ripple is high, which means that CIC doesnot good for wide-band DDC filtering. I wana implement a wide-band DDC, e.g., IF center frequncy is 20MHz, the signal bandwidth is 10MHz, the AD converter sampling frequency is 80MHz, in order to filtering the signal out, there need a -80dB attenuation on stopband out of 10MHz. Thanks Sun Lei. "arun" <arun.umapathy@wipro.com> ??????:1167728931.852911.26380@v33g2000cwv.googlegroups.com...> Hi, > > For IF DDC converter you can go with CIC filter followed by FIR > filter. CIC filter does most of the decimation for you, and for the > out-of-band suppression you can go with the FIR filter. > CIC filter does not need any multipliers.... > You can find lot of materials relating to design of CIC filter on the > net. > > Best Regards, > Arun > > SunLei wrote: >> hi, >> >> On the FPGA implementation of decimation filters, which type of >> decimate >> filters do you prefer? >> >> I am designing a IF DDC converter, and wana use FPGA to implement the >> decimate filter, but I found the Half-band lowpass and the euipripple fir >> filters can hardly stop the out-band below -80dB. I wish to stop the >> outband >> under -90dB, and the Chebyshev filter can, but it's not stable because >> it's >> IIR, so I appreciate FIR filters. >> >> Any suggestions? >> >> Sun Lei. >

Reply by ●January 3, 20072007-01-03

To implement a wide-band DDC, e.g., IF center frequncy is 20MHz, the signal bandwidth is 10MHz, the AD converter sampling frequency is 80MHz, in order to filtering the signal out, there need a -80dB attenuation on stopband out of 10MHz. A filter before decimation is inevitable, and if the stopband attenuation is not enough, there is always a small folded frequency in band, like a interface or harmonics. It's easier to find and use a filter to simulate this conditions by Matlab. In my experiment, I tested several kinds of solutions. The CIC filter is good for FPGA implementation and high decimate rate, but not good for low decimate rate or wide-band filtering. The FIR filter is hardly to reject outband heavily.I mean in implementation issues, The FIR taps are restricted. In the spectrum analysis figure, the small 'interfere image peak' is obvious, if the attenuation is less than 60dB. The IIR filter can work better, but I am afraid it's not stable, because in my opions, it's a kind of unstable filter. Thanks. Sun Lei. "Tim Wescott" <tim@seemywebsite.com> ??????:Qr-dnfY8TZaFIwTYnZ2dnUVZ_v-tnZ2d@web-ster.com...> SunLei wrote: >> hi, >> >> On the FPGA implementation of decimation filters, which type of >> decimate filters do you prefer? > > The kind that are best for the project at hand. >> >> I am designing a IF DDC converter, and wana use FPGA to implement the >> decimate filter, but I found the Half-band lowpass and the euipripple fir >> filters can hardly stop the out-band below -80dB. > > Then you are using the wrong ones. Either of these topologies, given a > long enough filter and deep enough word lengths, can meet just about any > attenuation requirement you can cook up. > >> I wish to stop the outband under -90dB, and the Chebyshev filter can, but >> it's not stable because it's IIR, so I appreciate FIR filters. >> > IIR filters aren't _automatically_ unstable, they're just not guaranteed > to be stable. > >> Any suggestions? >> >> Sun Lei. > > I'm with Dirk. Tell us what you're _really_ thinking, and why you can't > do what you're trying to do with the tools that you have available. > > I suspect that you are laboring under one or both of the following two > problems: > > 1. You're a raw beginner at DSP stuff, and you're trying to do design > from inadequate cookbooks. This is inevitable, because cookbook design is > nearly always inadequate for DSP design. > > 2. You have a relatively small gap between your required filter bandwidth > and your required rejection band. This small gap is forcing you to seek a > filter with a very small shape factor, which isn't addressed by your > cookbooks. > > -- > > Tim Wescott > Wescott Design Services > http://www.wescottdesign.com > > Posting from Google? See http://cfaj.freeshell.org/google/ > > "Applied Control Theory for Embedded Systems" came out in April. > See details at http://www.wescottdesign.com/actfes/actfes.html

Reply by ●January 3, 20072007-01-03

SunLei wrote: (top posting fixed)> "Tim Wescott" <tim@seemywebsite.com> > ??????:Qr-dnfY8TZaFIwTYnZ2dnUVZ_v-tnZ2d@web-ster.com... > >>SunLei wrote: >> >>>hi, >>> >>> On the FPGA implementation of decimation filters, which type of >>>decimate filters do you prefer? >> >>The kind that are best for the project at hand. >> >>> I am designing a IF DDC converter, and wana use FPGA to implement the >>>decimate filter, but I found the Half-band lowpass and the euipripple fir >>>filters can hardly stop the out-band below -80dB. >> >>Then you are using the wrong ones. Either of these topologies, given a >>long enough filter and deep enough word lengths, can meet just about any >>attenuation requirement you can cook up. >> >> >>>I wish to stop the outband under -90dB, and the Chebyshev filter can, but >>>it's not stable because it's IIR, so I appreciate FIR filters. >>> >> >>IIR filters aren't _automatically_ unstable, they're just not guaranteed >>to be stable. >> >> >>> Any suggestions? >>> >>>Sun Lei. >> >>I'm with Dirk. Tell us what you're _really_ thinking, and why you can't >>do what you're trying to do with the tools that you have available. >> >>I suspect that you are laboring under one or both of the following two >>problems: >> >>1. You're a raw beginner at DSP stuff, and you're trying to do design >>from inadequate cookbooks. This is inevitable, because cookbook design is >>nearly always inadequate for DSP design. >> >>2. You have a relatively small gap between your required filter bandwidth >>and your required rejection band. This small gap is forcing you to seek a >>filter with a very small shape factor, which isn't addressed by your >>cookbooks. >> > To implement a wide-band DDC, e.g., IF center frequncy is 20MHz, > the signal bandwidth is 10MHz, the AD converter sampling frequency is > 80MHz, in order to filtering the signal out, there need a -80dB attenuation > on stopband out of 10MHz. > > A filter before decimation is inevitable, and if the stopband attenuation is > not enough, > there is always a small folded frequency in band, like a interface or > harmonics. > It's easier to find and use a filter to simulate this conditions by Matlab. > > In my experiment, I tested several kinds of solutions. > The CIC filter is good for FPGA implementation and high decimate rate, but > not good > for low decimate rate or wide-band filtering. > The FIR filter is hardly to reject outband heavily.I mean in implementation > issues, The > FIR taps are restricted. > In the spectrum analysis figure, the small 'interfere image peak' is > obvious, if the attenuation > is less than 60dB.Ah. 'in implementation issues'. That's informative. _What_ implementation issues? Are you restricted in the number of taps? Word length? What? Have you actually tried to see just how long and how precise a FIR filter you would need, _then_ checked if it's not possible, or have you just rejected it out of hand?> The IIR filter can work better, but I am afraid it's not stable, because in > my opions, it's > a kind of unstable filter.In your opinion? Have you looked at any math books lately? IIR filters (note the plural, there isn't just one) can easily be unstable if you're not careful, but they can also be as stable as rocks if you pay attention. I think you are over constraining yourself. You've started by rejecting things, but now you're sitting in an empty room with no tools. Now it's time to jump into your dumpster and pull all those rejected tools out, and ask yourself "what do I need to do with _this_ tool to make it good enough". If your FIR filters are too long, can you cascade them? Have you considered that if you're decimating you don't have to calculate the whole filter for each input? Could you learn how to design stable IIR filters, and either cascade them with FIR filters or use them as-is? Could you use some CIC stages, then cascade that with a FIR filter to correct the passband ripple, either before or after sampling? -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ "Applied Control Theory for Embedded Systems" came out in April. See details at http://www.wescottdesign.com/actfes/actfes.html

Reply by ●January 4, 20072007-01-04

Yes, I will try on your suggestions later. Maybe there are some misunderstanding between us, mainly because my un-excactly word expressions. I don't know if there is a method to upload figures, if so, I can depict the question a little more clear. Thank you ! Sun Lei. "Tim Wescott" <tim@seemywebsite.com> ??????:3pGdnfLyvYFcTgbYnZ2dnUVZ_sqdnZ2d@web-ster.com...> SunLei wrote: > > (top posting fixed) > >> "Tim Wescott" <tim@seemywebsite.com> >> ??????:Qr-dnfY8TZaFIwTYnZ2dnUVZ_v-tnZ2d@web-ster.com... >> >>>SunLei wrote: >>> >>>>hi, >>>> >>>> On the FPGA implementation of decimation filters, which type of >>>> decimate filters do you prefer? >>> >>>The kind that are best for the project at hand. >>> >>>> I am designing a IF DDC converter, and wana use FPGA to implement >>>> the decimate filter, but I found the Half-band lowpass and the >>>> euipripple fir filters can hardly stop the out-band below -80dB. >>> >>>Then you are using the wrong ones. Either of these topologies, given a >>>long enough filter and deep enough word lengths, can meet just about any >>>attenuation requirement you can cook up. >>> >>> >>>>I wish to stop the outband under -90dB, and the Chebyshev filter can, >>>>but it's not stable because it's IIR, so I appreciate FIR filters. >>>> >>> >>>IIR filters aren't _automatically_ unstable, they're just not guaranteed >>>to be stable. >>> >>> >>>> Any suggestions? >>>> >>>>Sun Lei. >>> >>>I'm with Dirk. Tell us what you're _really_ thinking, and why you can't >>>do what you're trying to do with the tools that you have available. >>> >>>I suspect that you are laboring under one or both of the following two >>>problems: >>> >>>1. You're a raw beginner at DSP stuff, and you're trying to do design >>>from inadequate cookbooks. This is inevitable, because cookbook design >>>is nearly always inadequate for DSP design. >>> >>>2. You have a relatively small gap between your required filter >>>bandwidth and your required rejection band. This small gap is forcing >>>you to seek a filter with a very small shape factor, which isn't >>>addressed by your cookbooks. >>> >> To implement a wide-band DDC, e.g., IF center frequncy is 20MHz, >> the signal bandwidth is 10MHz, the AD converter sampling frequency is >> 80MHz, in order to filtering the signal out, there need a -80dB >> attenuation >> on stopband out of 10MHz. >> >> A filter before decimation is inevitable, and if the stopband attenuation >> is not enough, >> there is always a small folded frequency in band, like a interface or >> harmonics. >> It's easier to find and use a filter to simulate this conditions by >> Matlab. >> >> In my experiment, I tested several kinds of solutions. >> The CIC filter is good for FPGA implementation and high decimate rate, >> but not good >> for low decimate rate or wide-band filtering. >> The FIR filter is hardly to reject outband heavily.I mean in >> implementation issues, The >> FIR taps are restricted. >> In the spectrum analysis figure, the small 'interfere image peak' is >> obvious, if the attenuation >> is less than 60dB. > > Ah. 'in implementation issues'. That's informative. > > _What_ implementation issues? Are you restricted in the number of taps? > Word length? What? > > Have you actually tried to see just how long and how precise a FIR filter > you would need, _then_ checked if it's not possible, or have you just > rejected it out of hand? > >> The IIR filter can work better, but I am afraid it's not stable, because >> in my opions, it's >> a kind of unstable filter. > > In your opinion? Have you looked at any math books lately? > > IIR filters (note the plural, there isn't just one) can easily be unstable > if you're not careful, but they can also be as stable as rocks if you pay > attention. > > I think you are over constraining yourself. You've started by rejecting > things, but now you're sitting in an empty room with no tools. Now it's > time to jump into your dumpster and pull all those rejected tools out, and > ask yourself "what do I need to do with _this_ tool to make it good > enough". > > If your FIR filters are too long, can you cascade them? Have you > considered that if you're decimating you don't have to calculate the whole > filter for each input? > > Could you learn how to design stable IIR filters, and either cascade them > with FIR filters or use them as-is? > > Could you use some CIC stages, then cascade that with a FIR filter to > correct the passband ripple, either before or after sampling? > > -- > > Tim Wescott > Wescott Design Services > http://www.wescottdesign.com > > Posting from Google? See http://cfaj.freeshell.org/google/ > > "Applied Control Theory for Embedded Systems" came out in April. > See details at http://www.wescottdesign.com/actfes/actfes.html

Reply by ●January 4, 20072007-01-04

SunLei wrote: (top posting fixed)> > "Tim Wescott" <tim@seemywebsite.com> > ??????:3pGdnfLyvYFcTgbYnZ2dnUVZ_sqdnZ2d@web-ster.com... > >>SunLei wrote: >> >>(top posting fixed) >> >> >>>"Tim Wescott" <tim@seemywebsite.com> >>>??????:Qr-dnfY8TZaFIwTYnZ2dnUVZ_v-tnZ2d@web-ster.com... >>> >>> >>>>SunLei wrote: >>>> >>>> >>>>>hi, >>>>> >>>>> On the FPGA implementation of decimation filters, which type of >>>>>decimate filters do you prefer? >>>>-- snip -->>Could you learn how to design stable IIR filters, and either cascade them >>with FIR filters or use them as-is? >> >>Could you use some CIC stages, then cascade that with a FIR filter to >>correct the passband ripple, either before or after sampling? >> > > Yes, I will try on your suggestions later. > Maybe there are some misunderstanding between us, mainly because my > un-excactly word expressions. I don't know if there is a method to upload > figures, if so, I can depict the question a little more clear. >.--------. | | | Try | --------->| this |----------> | one. | | | '--------' (created by AACircuit v1.28.6 beta 04/19/05 www.tech-chat.de) It's still ASCII text, but it will do for simple diagrams. If you have a web site you can also post your diagram to it in .pdf or as a picture, and include a link. There are web sites out there that let you post a picture and give you a link, then force us to look at ads when we look at it -- I have no idea how to use those, since I have my own site. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ "Applied Control Theory for Embedded Systems" came out in April. See details at http://www.wescottdesign.com/actfes/actfes.html

Reply by ●January 4, 20072007-01-04

A few points: 1) A CIC filter does not have pass-band ripple. It has a sin(x)/x droop, but no ripple. 2) The usual set-up is to follow the CIC with a decimating FIR filter or FIR filter bank to narrow the bandwidth to a small fraction (less than 1/4) of the CIC main lobe width and to flatten the passband response. The advantage of using the CIC is the CIC's response referred to the output sample rate is nearly independent of the decimation ratio. That allows you to use a fixed FIR filter or Filter bank (fixed meaning you do not have to adjust the coefficients when you change the decimation ratio) after the CIC. This scheme works fine even with small (e.g. decimate by 1 or 2) decimation ratios in the CIC since the pass band shaping is handled by the FIR filter and the CIC is simply doing the pre-decimating and pre-filtering to get rid of images. IIR filters are often not appropriate in a DDC because it is difficult to make them stable, linear phase AND work over a large range of decimation ratios all at the same time. For digital comm, non-linear phase alone can be a deal-killer.